1. Technical Field
Embodiments of the invention relate to an active control device and a semiconductor device including the same, and more particularly to a technology for controlling an active command in response to a pin/pad change of a command address.
2. Description of Related Art
Typically, a semiconductor memory device includes a plurality of banks. Each bank is a functional unit capable of performing independent access, and includes a memory cell array, a sense-amplifier (sense-amp) array, an address decoder, etc.
Generally, when accessing a specific memory cell of a specific bank, an active command for controlling a row line is applied to the specific memory cell of the specific bank so as to activate a row line (word line) of the corresponding bank. Subsequently, read/write commands for controlling a column line are applied to the memory cell so that sense-amplifying and restoring processes of a specific column (bit line) are carried out. Thereafter, after completion of the operation for accessing the corresponding bank, a precharge command is applied to the memory cell such that a row line of the corresponding bank is deactivated.
The semiconductor memory device may generate an internal command signal by combining external commands, for example, a chip selection signal (/CS), a RAS signal (/RAS), a CAS signal (/CAS), a write enable signal (/WE), etc. A circuit for generating an internal command signal is referred to as a command decoder.
However, a chip size is gradually reduced according to a tech-shrink, such that the number of pads is also gradually reduced in proportion to the reduced chip size. In addition, many people and developers are conducting intensive research into a method for reducing production costs by reducing the number of wire bonding pins during packaging of the semiconductor device as the number of channels is gradually reduced. However, in order to reduce the number of wire bonding pins, there is a need to reduce the number of command address pins.
If the number of command address pins is reduced, the amount of input data capable of being simultaneously received is reduced. Accordingly, several command signals should be input to the semiconductor memory device over time such that the corresponding address can be applied to the semiconductor memory device.
For example, a row address RA<0:14>, a bank address BA<0:2>, and an active command address ADD<0:N> should be applied to at least LPDDR4 specification of 8-bank device having 8 gigabits density. In this case, if the number of command address pins is reduced to 8 pins, the active command must be input to the semiconductor memory device for a minimum of 4 clocks in such a manner that a row active command can be normally input and a desired address can be selected.
The conventional semiconductor device is configured to perform a row access operation by only one active command. However, at least two active commands in response to the reduced number of command address pins should be applied to the conventional semiconductor device so as to perform the row address operation.